Now Reading
Industry’s first low-power PCI Express Gen 4 buffers raise the bar in power and performance

Industry’s first low-power PCI Express Gen 4 buffers raise the bar in power and performance

Posted by Zenobia HegdeMarch 16, 2018

Silicon Labs has introduced a new family of low-power PCI Express® (PCIe®) Gen 1/2/3/4 clock buffers that provide ultra-low jitter clock distribution in 1.5 V and 1.8 V applications. With additive jitter performance of 40 fs RMS (typical), Silicon Labs’ new Si532xx PCIe clock buffers provide more than 90% margin to stringent PCIe Gen 3 and Gen 4 jitter specifications, simplifying clock distribution and de-risking product development.

Increasingly, data centre hardware designs including network interface cards (NICs), PCIe bus expanders and high-performance computing (HPC) accelerators are using low-power 1.5 V or 1.8 V supplies to minimise overall power consumption.

Powered from a single 1.5 V-1.8 V supply and featuring up to 12 clock outputs, the Si532xx buffers are ideally suited to provide low-jitter PCIe clock distribution in low-power designs. The Si532xx clocks support PCIe Common Clock, Separate Reference No Spread (SRNS) and Separate Reference Independent Spread (SRIS) architectures, enabling them to be used in a wide variety of applications.

The Si532xx device output drivers leverage Silicon Labs’ push-pull HCSL technology, which eliminates the need for external termination resistors required by conventional PCIe buffers using constant-current output driver technology. Internal power filtering prevents power supply noise from degrading clock jitter performance, eliminating discrete low-dropout regulators required by competing solutions. The Si532xx family supports both 85 ohm and 100 ohm impedance options.

“We’ve leveraged Silicon Labs’ expertise in high-performance clock design to reduce jitter and power consumption in PCIe clock distribution applications,” said James Wilson, senior marketing director for Silicon Labs’ timing products. “Our new Si532xx family demonstrates Silicon Labs’ commitment to help consolidate and simplify high-speed clock tree designs in data centre, industrial, communications and consumer designs.”

Because clock jitter is a critical design parameter for all PCIe applications, Silicon Labs offers PCIe Gen 1/2/3/4 software that simplifies PCIe jitter measurements. This easy-to-use utility is available for developers to download.

Pricing and availability

Samples and production quantities of the Si532xx PCIe clock buffers are available now in multiple output options. The Si53212, Si53208 and Si53204 clocks provide twelve, eight and four PCIe clock outputs. Samples ship in two weeks, and production quantities are available in four weeks. Pricing in 10,000-unit quantities ranges from US$1.40 (€1.14) for the 4-output device to US$2.17 (€1.76) for the 12-output clock.

Silicon Labs’ new Si53204-EVB development kit, priced at US$175 (€142.08), provides quick, simple PCIe buffer evaluation. For more information about the Si532xx PCIe buffer family or to order samples and development kits,click here.

Comment on this article below or via Twitter: @IoTNow_OR @jcIoTnow

About The Author
Zenobia Hegde

Leave a Response