Cadence Design Systems, Inc. has announced the LPDDR5X memory interface IP design optimised to operate at 8533Mbps up to 33% faster than the previous generation of LPDDR IP. Available now for customer engagements, the Cadence LPDDR5X IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful LPDDR5 and GDDR6 product lines. The new Cadence LPDDR5X memory IP solution consists of a silicon-proven PHY and high-performance controller designed to connect to LPDDR5X DRAM devices that follow the JEDEC JESD209-5B standard. The controller/PHY interface is based on the latest DFI 5.1 specification, and a variety of on-chip buses are supported.
LPDDR5X memory opens up a wide variety of high-bandwidth applications beyond the mobile market traditionally served by LPDDR memory, including advanced driver assistance systems (ADAS), autonomous driving, lower-end edge AI and networking. Cadence LPDDR5X IP is designed to enable the SoC designs for these and other applications with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.
Cadence design IP supports the fastest data rate defined by the JEDEC standard (JESD209-5B). Cadence’s LPDDR5X Controller and PHY have been verified with Cadence’s Verification IP (VIP) for LPDDR5X to provide rapid IP and SoC verification closure. Cadence VIP for LPDDR5X includes a complete solution from IP to system-level verification with DFI VIP, LPDDR5X memory model and System Performance Analyser.
“LPDDR5X’s peak speeds will raise the bar for device experiences and performance at the edge, from automotive to consumer IoT to networking devices,” says Michael Basca, vice president of products and systems in Micron’s Embedded Business Unit. “Our collaboration with Cadence will accelerate ecosystem adoption of LPDDR5X by enabling the next wave of chipsets to work seamlessly with this low-power, high-performance memory.”
“Cadence LPDDR5X IP operating at 8533Mbps in silicon showcases Cadence’s next-generation architecture for complete memory system IP solutions,” notes Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “This new memory IP solution solidifies our memory interface IP leadership by enabling the industry’s future AI, automotive and mobile SoC designs today.”
The LPDDR5X IP supports Cadence’s Intelligent System Design strategy, which enables SoC design excellence with high-performance, design-optimised, technology.
For more information on the LPDDR5X IP, please visit here.
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